How much current can a single PCB via carry?

A standard 0.3 mm drill via with 25 µm plating on a 1.6 mm board can safely carry about 0.5–1 A depending on allowable temperature rise. Larger drill sizes and thicker plating increase capacity significantly.

How do you calculate via resistance?

R_via = ρ × L / A, where ρ is copper resistivity (~1.724 µΩ·cm at 20 °C), L is the board thickness (via barrel length), and A is the cross-sectional area of the copper barrel: A = π × (D² − d²) / 4.

What is via barrel copper area?

The barrel area is the annular ring of copper plated inside the drilled hole: A = π × [(drill/2)² − ((drill/2) − plating)²]. For a 0.3 mm drill with 25 µm plating: A ≈ 0.0216 mm².

Why use a via array instead of a single via?

A single via may not carry enough current for power connections. An array of parallel vias shares the current, reducing resistance and voltage drop proportionally. Arrays also improve thermal performance.

What derating factor should I use for via arrays?

Adjacent vias heat each other, reducing individual capacity. A derating factor of 0.7–0.85 is common. Wider spacing (≥ 3× drill diameter) reduces thermal coupling and allows higher derating.

What via plating thickness is standard?

IPC Class 2 requires a minimum of 20 µm (0.8 mil) average plating. Most fabricators deliver 25 µm (1 mil) standard. Class 3 (high reliability) requires 25 µm minimum.

How does board thickness affect via resistance?

Via resistance is directly proportional to barrel length (board thickness). A 3.2 mm board has twice the via resistance of a 1.6 mm board for the same drill and plating.

What is the difference between through-hole, blind, and buried vias?

Through-hole vias span the entire board. Blind vias connect an outer layer to one or more inner layers. Buried vias connect only inner layers. Blind and buried vias are shorter, so they have lower resistance but cost more to fabricate.

How many vias do I need for a 5 A power connection?

If each 0.3 mm via safely carries ~0.7 A (with derating), you need at least 8 vias for 5 A (5/0.7 ≈ 7.1, round up). Larger 0.4 mm or 0.5 mm vias carry more current and reduce the count.

PCB Via Array & Current Capacity Calculator – IPC-2152 Via Resistance & Thermal Headroom

⚙️ Input Parameters

⚡Total System Current (I)

🌡️Allowed Temp Rise (ΔT)

°C

⊙Via Drill Diameter (d)

⚡Plating Thickness (t)

🔲PCB Layer

🗂️Number of Vias (N)

vias

📚Board Thickness

🌡️Ambient Temperature

°C

I_via = k · ΔT^0.44 · A^0.725

IPC-2152 single-via current (A in mil²)

I_array = I_via × N

Total array capacity

📋 TOP VIEW (Via Grid Array)

🔍 CROSS SECTION (Via Stackup)

ℹ️

Array of 10 vias carries up to 19.50 A safely with +30% thermal headroom.

📊 Results

Max Current / Via (I_via)

1.95 A

Total Array Capacity

19.50 A

Array Thermal Headroom

+30%

Safety Factor

1.30

Array Via Resistance

0.15 mΩ

Array Voltage Drop (ΔV)

2.25 mV

📐 Via Spacing Guidelines

Green: > 3d

Excellent thermal isolation

Orange: 2d – 3d

Acceptable mutual coupling

Red: < 2d

Excessive thermal coupling

⚙️ Calculation Steps

Compute via barrel copper area: A = π × t × (d − t)

Convert area to mil² and apply IPC-2152: I_via = k × ΔT^0.44 × A^0.725

Total array capacity: I_array = I_via × N

Thermal headroom: (I_array − I_system) / I_system × 100%

Single via resistance: R = ρ × H / A; Array: R / N

Array voltage drop: ΔV = I_system × R_array

📊 Live Calculation

Step 1 — Via Copper Area

A = π × 0.025 × 0.275 = 0.0216 mm² = 33.5 mil²

Step 2 — Single Via Current

I_via = 0.040 × 20^0.44 × 33.5^0.725 = 1.95 A

Step 3 — Array Capacity & Headroom

I_array = 1.95 × 10 = 19.50 A | Headroom = +30%

Step 4 — Resistance & Voltage Drop

R_array = 0.15 mΩ | ΔV = 15 × 0.15m = 2.25 mV

📋 Quick Via Reference

1 oz copper plating = 35 µm
2 oz copper plating = 70 µm
1 mil = 0.0254 mm = 25.4 µm
Keep via voltage drop < 3% for best power delivery
Use more vias or thicker plating to reduce resistance and heat

💡 Typical Recommendations

Application	Recommended Vias
Power Plane	Many (8–20+)
Signal Via	Minimal (1–2)
Thermal Pad	Grid array (safety margin)

ℹ️

Proper via array design prevents excessive heating and ensures reliable power delivery. Use solid copper connections and adequate spacing for power and thermal vias. For accurate results, refer to the IPC-2152 standard.

PCB Via Array & Current Capacity Calculator — Complete IPC-2152 Guide

This PCB via array calculator determines the safe current per via, total array current capacity, via barrel resistance, voltage drop, and thermal headroom for any combination of drill size, plating thickness, board thickness, and number of vias. It applies IPC-2152 thermal principles so you can confidently size via arrays for power connections, ground stitching, and thermal management without risking barrel failure or excessive heating.

Via Current Capacity Formula

Barrel copper area: A = π × [(D/2)² − ((D/2) − t_plating)²]

Via resistance: R_via = ρ(T) × L_board / A

Current per via: I_via = J_max × A (typical J_max ≈ 20–30 A/mm²)

Array capacity: I_total = I_via × N × derating

Via Size & Current Reference Table

Drill Dia (mm)	Plating (µm)	Barrel Area (mm²)	R_via (mΩ) @ 1.6mm	Safe Current (A)*
0.2	25	0.0137	20.1	0.3
0.3	25	0.0216	12.8	0.5
0.4	25	0.0294	9.4	0.7
0.5	25	0.0373	7.4	0.9
0.6	25	0.0451	6.1	1.1
0.8	25	0.0608	4.5	1.5
1.0	25	0.0765	3.6	1.9

* Safe current at ΔT ≈ 10 °C, 20 °C ambient. Derate for arrays (×0.7–0.85) and higher temperature.

Worked Examples

🔧 Example 1 — 5 A Power Via Array (0.4 mm drill, 1.6 mm board)

GivenI = 5 A, drill = 0.4 mm, plating = 25 µm, board = 1.6 mm, derating = 0.8

Step 1A = π × [(0.2)² − (0.175)²] = 0.0294 mm²

Step 2I_via = 0.7 A (from table) × 0.8 derating = 0.56 A per via

Step 3Vias needed = ceil(5 / 0.56) = 9 vias minimum

Step 4R_array = 9.4 mΩ / 9 = 1.04 mΩ | V_drop = 5 × 0.00104 = 5.2 mV

Result9 vias minimum | R = 1.04 mΩ | V_drop = 5.2 mV — negligible

⚡ Example 2 — Ground Stitching Array (20 vias, 0.3 mm drill)

Given20 × 0.3 mm vias, plating = 25 µm, board = 1.6 mm, T = 60 °C

Step 1ρ(60°C) = 1.724 × 1.157 = 1.995 µΩ·cm

Step 2R_via = 1.995e-6 × 0.16 / 2.16e-4 = 14.8 mΩ per via

Step 3R_array = 14.8 / 20 = 0.74 mΩ

Step 4Total capacity = 0.5 A × 20 × 0.75 = 7.5 A

ResultArray capacity ≈ 7.5 A | R_array = 0.74 mΩ — excellent for ground stitching

Via Types Comparison

Via Type	Spans	Barrel Length	Resistance	Cost	Use Case
Through-hole	All layers	Full board thickness	Highest	Standard	General routing, power
Blind	Outer → inner	Partial	Lower	2–3× standard	HDI, BGA escape
Buried	Inner → inner	Partial	Lowest	3–5× standard	High-layer-count HDI
Microvia	1 layer span	Minimal	Very low	Laser drill	Fine-pitch BGA

IPC Plating Thickness Standards

IPC Class	Min Average Plating	Min at Any Point	Application
Class 1	20 µm (0.8 mil)	18 µm	Consumer electronics
Class 2	20 µm (0.8 mil)	18 µm	Industrial, telecom (most common)
Class 3	25 µm (1.0 mil)	20 µm	Military, aerospace, medical

Design Guidelines

Power vias: Use arrays of 0.4–0.5 mm vias. Always calculate total current capacity with 0.7–0.85 derating.
Ground stitching: Place vias around the perimeter and at critical return-path points; spacing ≤ λ/20 at the highest frequency.
Via spacing: ≥ 3× drill diameter reduces thermal coupling; ≥ 5× gives near-independent thermal behavior.
Thermal vias: Under power pads and thermal slugs, use filled or capped vias to conduct heat to inner planes.
Redundancy: Add 20–30% more vias than the minimum to account for manufacturing variation and long-term reliability.

Frequently Asked Questions

How many vias do I need for 10 A?

With 0.4 mm drill vias (0.56 A each derated), you need ceil(10/0.56) = 18 vias. Using 0.5 mm drill (0.72 A derated) reduces this to 14 vias. Larger vias = fewer needed.

Does via-in-pad affect current capacity?

Via-in-pad places the via directly in the component pad. If filled and capped, it performs the same electrically. If open (not filled), solder can wick down the barrel, potentially creating a weak joint but not significantly affecting current capacity.

Can I use one large via instead of many small ones?

Yes, but a single large via is mechanically weaker and harder to plate uniformly. Arrays of smaller vias provide more total barrel area, better reliability, and distribute thermal stress.

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